1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and more particularly, to a wafer test trigger signal generating circuit, a wafer test circuit using the same, and a semiconductor memory apparatus having the same.
2. Related Art
In general, when a semiconductor memory apparatus is tested in a wafer state, the semiconductor memory apparatus enters various test modes by using a plurality of specific addresses. For example, the semiconductor memory apparatus enters the various test modes by setting one of specific address signals ‘add<0:4>’ as a trigger signal ‘add<4>’ and decoding remaining specific address signals ‘add<0:3>’. Here, the trigger signal ‘add<4>’ serves as a factor to determine the decoding timing of the remaining specific address signals ‘add<0:3>’. The trigger signal ‘add<4>’ is controlled by a test apparatus such that the trigger signal ‘add<4>’ can be enabled at the center of the pulse of the remaining specific addresses ‘add<0:3>’.
In order to allow the semiconductor memory apparatus of the wafer state to enter the test modes by using the test apparatus, connection lines are necessary to connect the test apparatus to the semiconductor memory apparatus.
FIG. 1 is a timing diagram showing conventional address skews input into a semiconductor memory apparatus of a wafer state from a test apparatus. In FIG. 1, when the first address signal ‘add<0>’ is transitioned to a high level, the second to fourth address signals ‘add<1>, add<2>’, and ‘add<3>’ must be also transitioned to a high level. However, due to the characteristics of the test apparatus, it is difficult to precisely determine the transition timing of the first to fourth address signals ‘add<0>’ to ‘add<3>’ input into the semiconductor memory apparatus.
In addition, the test apparatus must control the transition timing of the first to fourth address signals ‘add<0>’ to ‘add<3>’ by taking into consideration characteristics of the lines connected to the semiconductor memory apparatus and the test apparatus, so it is more difficult to precisely determine the transition timing of the first to fourth address signals add ‘<0>’ to ‘add<3>’.
In FIG. 1, if a skew (deviation of transition timing) of the second to fourth address signals ‘add<1>, ‘add<2>’, and ‘add<3>’ occurs on the basis of the first address signal ‘add<0>’ and a skew of a signal used as a trigger signal ‘add<4>’ occurs, then the semiconductor memory apparatus may not enter the test mode required by a tester. By way of the example described below and shown in FIG. 1, a presumption is made that the tester introduces the semiconductor memory apparatus into the test mode in which the first to fourth address signals ‘add<0>’ to ‘add<3>’ are set to a high level.
In FIG. 1, situation A including the trigger signal ‘add<4>’ being transitioned in the normal timing even if the skew of the first to fourth address signals ‘add<0>’ to ‘add<3>’ occurs. Accordingly, in a state in which the first to fourth address signals ‘add<0>’ to ‘add<3>’ are set to a high level, the first to fourth address signals ‘add<0>’ to ‘add<3>’ are decoded so that the semiconductor memory apparatus can enter the test mode required by the tester.
In situations B and C, the skew of the first to fourth address signals ‘add<0>’ to ‘add<3>’ occurs and the skew of the trigger signal ‘add<4>’ also occurs. In the situation B, the semiconductor memory apparatus enters the test mode under the condition that the first address signal ‘add<0>’ is at a high level, the second address signal ‘add<1>’ is at a high level, the third address signal ‘add<2>’ is at a low level, and the fourth address signal ‘add<3>’ is at a high level. In the situation C, the semiconductor memory apparatus enters the test mode under the condition that the first address signal ‘add<0>’ is at a high level, the second address signal ‘add<1>’ is at a low level, the third address signal ‘add<2>’ is at a high level, and the fourth address signal ‘add<3>’ is at a high level.
Thus, the wafer test circuit of the semiconductor memory apparatus, which is generally used to allow the semiconductor memory apparatus of the wafer state to enter the test mode, cannot enter the test mode required by the tester, so that the test time and the test cost may increase.
Accordingly, one of the specific addresses must be used as the trigger signal and the remaining specific addresses must be decoded in order to allow the semiconductor memory apparatus of the wafer state to enter the test mode. Here, the semiconductor memory apparatus receives the address used as the trigger signal and the addresses to be decoded from the test apparatus through lines. Thus, as shown in FIG. 1, due to the characteristics of the lines that connect the test apparatus to the semiconductor memory apparatus, the semiconductor memory apparatus cannot enter the test mode required by the tester if the skew between the address used as the trigger signal and the addresses to be decoded becomes severe.